Single-Core Compatibility Mode

Single-Core Compatibility Mode enables migration of existing PxMM (first-generation) projects to the PCMM2G platform.

Configuration: This setting is enabled for each project.
- See Configure Project Settings.
Execution Behavior: This mode forces the motion engine and PLC virtual machine to run on the same core, emulating single-core controller behavior.
No Code Changes Required: Applications originally designed for single-core execution run without modification.
Diagnostics Support and Persistence: A warning message is logged at project startup when the compatibility mode is enabled to aid in diagnostics.
- This setting persists across firmware updates and controller backup/restore operations.
Customer Benefit: Allows continued use of existing applications without the need for immediate code refactoring, easing the transition to multi-core platforms.

Limitations and Guidelines

This mode preserves compatibility with legacy applications but exhibits operational characteristics that differ from both first-generation controllers and native PCMM2G multi-core operation.

Operational Behavior
Impact on Migrated Applications
Application Guidelines
- Recommendations

Operational Behavior

In Single-Core Compatibility Mode:

The PCMM2G controller does not interrupt PLC code execution when the next motion cycle begins.
The controller continues executing PLC logic until completion, regardless of cycle time boundaries.
This differs from first-generation AKD PDMM / PCMM controllers, where the PLC VM is suspended if execution exceeds the available cycle time.

When PLC execution exceeds the motion cycle time:

EtherCAT communication is delayed until PLC logic completion.
The controller reports late Tx/Rx messages.
Distributed clock synchronization is affected.
E30 errors are likely to occur.

Figure 1: Example: SCCM Overloaded Cycle

Impact on Migrated Applications

The PCMM2G provides significantly higher processing performance than first-generation hardware.

Applications that operate within timing constraints on PxMM controllers typically execute with greater timing margin on PCMM2G hardware.

Timing issues may occur when:

Additional PLC logic increases execution time beyond the original application scope.
EtherCAT cycle time settings are aggressive relative to total workload.
Complex computational tasks are added to migrated code.

Application Guidelines

Single-Core Compatibility Mode is appropriate for:

Migration of existing PxMM controller projects to PCMM2G.
Applications where minimizing code modification is required.
Maintaining legacy application behavior during hardware transition.

Multi-core compatible execution is recommended for:

New projects developed on PCMM2G hardware.
Applications requiring significant functional expansion.
Projects where maximum performance and scalability are required.

Recommendations

Kollmorgen strongly recommends updating PLC code for multi-core compatibility when migrating existing code to new projects that increases controller workload.

Mitigation Options

If timing constraints are encountered in Single-Core Compatibility Mode, consider these mitigation options:

Code Optimization: Reduce computational complexity in PLC logic.
Update the Program Cycle settings: See Program a Multi-Core Controller.
Cycle Time Adjustment: Increase EtherCAT cycle time if application requirements allow it.
Multi-Core Migration: Update application to use multi-core compatible guidelines.
- See Define the PLC Cycle.