DRV.EMUEPULSEWIDTH
Description
EMU Encoder Out PulseWhen the step gets activated, the action is activated for a single execution, and possibly once again when the step is deactivated Width Register
Sets pulse width for CW/CCW and Step and Direction modes. This parameter does not effect the A quad B mode. To calculate emuOutPulseWidth:
(Desired pulse width -40 nsec)/520 nsec
Requirement | DSFPGA-03-306 | |
Bits | Bits | Description |
11:0 | emuOutPulseWidth | Read/Write 12 bit unsigned number minimum resolution is 520 nsec. Reset state – 0 |
15:12 | reserved |
- Register is in counts (12 bit)
- Register * 520ns + 40ns is the actual pulse with.
- Register = 1 = pulse width is 560ns = 0.56us (minimum value)
- For each register increment the pulse width is raised by 0.52us
Example
50 usecs pulse width
emuOutPulseWidth = (50 usecs – 40 nsec)/520 nsec = 96
actual pulse = 96*520 nsec + 40 nsec = 49.88 usecs.
General Information
Type |
TBD |
Units |
us(microseconds) |
Range |
4.08 us to 2621.48 us |
Default Value |
4.08 us |
Data Type |
Float |
Start Version |
M_01-00-00-000 |
Index/Subindex |
Object Start Version |
|
---|---|---|
/0 |
M_01-00-00-000 |
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